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I am having trouble learning how to model n bit wide mux's in verilog.
Remember this? RTL is an acronym for register transfer level. This implies that your Verilog code describes how data is transformed as it is passed from register to register. The transforming of the data is performed by the combinational logic that exists between the registers. Now for the MUX2 design. In the above code. Learn about designing a multiplexer in verilog with example code, specifically a 4x1 or 4 to 1 mux. What is a mux or multiplexer? A multiplexer or mux in short, is a digital element that transfers data from one of the N inputs to the output based on the select signal. The case shown below is when N equals 4.
I am trying to gate level model a 2 bit wide multiplexer, here is my current code:
I am receiving the following error messages:
Can anyone help me out or point me in the right direction for some easy understanding of how to implement this?
TomTom
2 Answers
Multi-bit buses are declared like this
![8 to 1 mux verilog 8 to 1 mux verilog](http://electrosofts.com/verilog/mux_circuit.jpg)
and not like this
mkrieger1mkrieger1
Besides the bus declaration issue described by mkrieger1 you have several other issues that you need to take care of.
Currently you have multiple drivers on t0 and t1. It appears from the logic that you want t0 and t1 to be 2 bit buses as well, but you are using an implicit declaration of those signals which will create single bit signals. For example that means that these two instances are both driving the same signal:
In this case you will get an X value whenever these gates differ in their output.
If instead you declared these signals and make them 2 bits, then the following would work as you want:
Then you have the issue of doing multiple bit implementations using a gate, specifically the OR gate. A simple gate only works with one bit outputs, but they can work on an array. That is done by declaring an array of instances. You haven't used instance names, but to accomplish this you will need an instance name and a range declaration. The following would work for your OR gate:
That will perform the operation on both bits of those 3 signals.
Overall the most compact implementation would be something like:
In this case I've also used the array form for the AND gates. In this case note that they are 2 bits wide, but the s and sbar inputs are just one bit wide. Verilog handles that by using those one bit signals for all the bits of the gate.
Brad BudlongBrad Budlong